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326 lines
17 KiB
326 lines
17 KiB
/**************************************************************************** |
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* drivers/net/cs89x0.h |
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* |
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* Copyright (C) 2009 Gregory Nutt. All rights reserved. |
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* Author: Gregory Nutt <gnutt@nuttx.org> |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* 3. Neither the name NuttX nor the names of its contributors may be |
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* used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED |
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************/ |
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#ifndef __DRIVERS_NET_CS89x0_H |
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#define __DRIVERS_NET_CS89x0_H |
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/**************************************************************************** |
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* Included Files |
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****************************************************************************/ |
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/**************************************************************************** |
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* Pre-processor Definitions |
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****************************************************************************/ |
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/* CONFIG_CS89x0_ALIGN16/32 determines if the 16-bit CS89x0 registers are |
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* aligned to 16-bit or 32-bit address boundaries. NOTE: If there multiple |
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* CS89x00 parts in the board architecture, we assume that the address |
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* alignment is the same for all implementations. If that is not the |
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* case, then it will be necessary to move a shift value into |
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* the cs89x0_driver_s structure and calculate the offsets dynamically in |
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* the putreg and getreg functions. |
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*/ |
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#if defined(CONFIG_CS89x0_ALIGN16) |
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# define CS89x0_RTDATA_OFFSET (0 << 1) |
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# define CS89x0_TxCMD_OFFSET (2 << 1) |
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# define CS89x0_TxLEN_OFFSET (3 << 1) |
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# define CS89x0_ISQ_OFFSET (4 << 1) |
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# define CS89x0_PPTR_OFFSET (5 << 1) |
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# define CS89x0_PDATA_OFFSET (6 << 1) |
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#elif defined(CONFIG_CS89x0_ALIGN32) |
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# define CS89x0_RTDATA_OFFSET (0 << 2) |
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# define CS89x0_TxCMD_OFFSET (2 << 2) |
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# define CS89x0_TxLEN_OFFSET (3 << 2) |
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# define CS89x0_ISQ_OFFSET (4 << 2) |
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# define CS89x0_PPTR_OFFSET (5 << 2) |
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# define CS89x0_PDATA_OFFSET (6 << 2) |
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#else |
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# error "CS89x00 address alignment is not defined" |
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#endif |
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/* ISQ register bit definitions */ |
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#define ISQ_EVENTMASK 0x003f /* Bits 0-5 indicate the status register */ |
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#define ISQ_RXEVENT 0x0004 |
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#define ISQ_TXEVENT 0x0008 |
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#define ISQ_BUFEVENT 0x000c |
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#define ISQ_RXMISSEVENT 0x0010 |
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#define ISQ_TXCOLEVENT 0x0012 |
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/* ISQ register TxEVENT bit definitions*/ |
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#define ISQ_RXEVENT_IAHASH (1 << 6) |
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#define ISQ_RXEVENT_DRIBBLE (1 << 7) |
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#define ISQ_RXEVENT_RXOK (1 << 8) |
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#define ISQ_RXEVENT_HASHED (1 << 9) |
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#define ISQ_RXEVENT_HASHNDX_SHIFT 10 |
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#define ISQ_RXEVENT_HASHNDX_MASK (0x3f << ISQ_RXEVENT_HASHNDX_SHIFT) |
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/* ISQ register TxEVENT bit definitions*/ |
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#define ISQ_TXEVENT_LOSSOFCRS (1 << 6) |
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#define ISQ_TXEVENT_SQEERROR (1 << 7) |
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#define ISQ_TXEVENT_TXOK (1 << 8) |
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#define ISQ_TXEVENT_OUTWINDOW (1 << 9) |
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#define ISQ_TXEVENT_JABBER (1 << 10) |
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#define ISQ_TXEVENT_NCOLLISION_SHIFT 11 |
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#define ISQ_TXEVENT_NCOLLISION_MASK (15 << ISQ_TXEVENT_NCOLLISION_SHIFT) |
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#define ISQ_TXEVENT_16COLL (1 << 15) |
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/* ISQ register BufEVENT bit definitions */ |
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#define ISQ_BUFEVENT_SWINT (1 << 6) |
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#define ISQ_BUFEVENT_RXDMAFRAME (1 << 7) |
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#define ISQ_BUFEVENT_RDY4TX (1 << 8) |
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#define ISQ_BUFEVENT_TXUNDERRUN (1 << 9) |
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#define ISQ_BUFEVENT_RXMISS (1 << 10) |
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#define ISQ_BUFEVENT_RX128 (1 << 11) |
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#define ISQ_BUFEVENT_RXDEST (1 << 15) |
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/* Packet page register offsets *********************************************/ |
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/* 0x0000 Bus interface registers */ |
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#define PPR_CHIPID 0x0000 /* Chip identifier - must be 0x630E */ |
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#define PPR_CHIPREV 0x0002 /* Chip revision, model codes */ |
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#define PPR_IOBASEADDRESS 0x0020 /* I/O Base Address */ |
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#define PPR_INTREG 0x0022 /* Interrupt configuration */ |
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# define PPR_INTREG_IRQ0 0x0000 /* Use INTR0 pin */ |
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# define PPR_INTREG_IRQ1 0x0001 /* Use INTR1 pin */ |
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# define PPR_INTREG_IRQ2 0x0002 /* Use INTR2 pin */ |
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# define PPR_INTREG_IRQ3 0x0003 /* Use INTR3 pin */ |
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#define PPR_DMACHANNELNUMBER 0x0024 /* DMA Channel Number (0,1, or 2) */ |
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#define PPR_DMASTARTOFFRAME 0x0026 /* DMA Start of Frame */ |
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#define PPR_DMAFRAMECOUNT 0x0028 /* DMA Frame Count (12-bits) */ |
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#define PPR_RXDMABYTECOUNT 0x002a /* Rx DMA Byte Count */ |
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#define PPR_MEMORYBASEADDRESS 0x002c /* Memory Base Address Register (20-bit) */ |
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#define PPR_BOOTPROMBASEADDRESS 0x0030 /* Boot PROM Base Address */ |
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#define PPR_BOOTPROMADDRESSMASK 0x0034 /* Boot PROM Address Mask */ |
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#define PPR_EEPROMCOMMAND 0x0040 /* EEPROM Command */ |
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#define PPR_EEPROMDATA 0x0042 /* EEPROM Data */ |
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#define PPR_RECVFRAMEBYTES 0x0050 /* Received Frame Byte Counter */ |
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/* 0x0100 - Configuration and control registers */ |
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#define PPR_RXCFG 0x0102 /* Receiver configuration */ |
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# define PPR_RXCFG_SKIP1 (1 << 6) /* Skip (discard) current frame */ |
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# define PPR_RXCFG_STREAM (1 << 7) /* Enable streaming mode */ |
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# define PPR_RXCFG_RXOK (1 << 8) /* RxOK interrupt enable */ |
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# define PPR_RxCFG_RxDMAonly (1 << 9) /* Use RxDMA for all frames */ |
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# define PPR_RxCFG_AutoRxDMA (1 << 10) /* Select RxDMA automatically */ |
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# define PPR_RxCFG_BufferCRC (1 << 11) /* Include CRC characters in frame */ |
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# define PPR_RxCFG_CRC (1 << 12) /* Enable interrupt on CRC error */ |
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# define PPR_RxCFG_RUNT (1 << 13) /* Enable interrupt on RUNT frames */ |
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# define PPR_RxCFG_EXTRA (1 << 14) /* Enable interrupt on frames with extra data */ |
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#define PPR_RXCTL 0x0104 /* Receiver control */ |
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# define PPR_RXCTL_IAHASH (1 << 6) /* Accept frames that match hash */ |
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# define PPR_RXCTL_PROMISCUOUS (1 << 7) /* Accept any frame */ |
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# define PPR_RXCTL_RXOK (1 << 8) /* Accept well formed frames */ |
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# define PPR_RXCTL_MULTICAST (1 << 9) /* Accept multicast frames */ |
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# define PPR_RXCTL_IA (1 << 10) /* Accept frame that matches IA */ |
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# define PPR_RXCTL_BROADCAST (1 << 11) /* Accept broadcast frames */ |
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# define PPR_RXCTL_CRC (1 << 12) /* Accept frames with bad CRC */ |
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# define PPR_RXCTL_RUNT (1 << 13) /* Accept runt frames */ |
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# define PPR_RXCTL_EXTRA (1 << 14) /* Accept frames that are too long */ |
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#define PPR_TXCFG 0x0106 /* Transmit configuration */ |
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# define PPR_TXCFG_CRS (1 << 6) /* Enable interrupt on loss of carrier */ |
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# define PPR_TXCFG_SQE (1 << 7) /* Enable interrupt on Signal Quality Error */ |
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# define PPR_TXCFG_TXOK (1 << 8) /* Enable interrupt on successful xmits */ |
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# define PPR_TXCFG_LATE (1 << 9) /* Enable interrupt on "out of window" */ |
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# define PPR_TXCFG_JABBER (1 << 10) /* Enable interrupt on jabber detect */ |
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# define PPR_TXCFG_COLLISION (1 << 11) /* Enable interrupt if collision */ |
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# define PPR_TXCFG_16COLLISIONS (1 << 15) /* Enable interrupt if > 16 collisions */ |
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#define PPR_TXCMD 0x0108 /* Transmit command status */ |
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# define PPR_TXCMD_TXSTART5 (0 << 6) /* Start after 5 bytes in buffer */ |
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# define PPR_TXCMD_TXSTART381 (1 << 6) /* Start after 381 bytes in buffer */ |
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# define PPR_TXCMD_TXSTART1021 (2 << 6) /* Start after 1021 bytes in buffer */ |
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# define PPR_TXCMD_TXSTARTFULL (3 << 6) /* Start after all bytes loaded */ |
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# define PPR_TXCMD_FORCE (1 << 8) /* Discard any pending packets */ |
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# define PPR_TXCMD_ONECOLLISION (1 << 9) /* Abort after a single collision */ |
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# define PPR_TXCMD_NOCRC (1 << 12) /* Do not add CRC */ |
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# define PPR_TXCMD_NOPAD (1 << 13) /* Do not pad short packets */ |
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#define PPR_BUFCFG 0x010a /* Buffer configuration */ |
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# define PPR_BUFCFG_SWI (1 << 6) /* Force interrupt via software */ |
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# define PPR_BUFCFG_RXDMA (1 << 7) /* Enable interrupt on Rx DMA */ |
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# define PPR_BUFCFG_TXRDY (1 << 8) /* Enable interrupt when ready for Tx */ |
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# define PPR_BUFCFG_TXUE (1 << 9) /* Enable interrupt in Tx underrun */ |
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# define PPR_BUFCFG_RXMISS (1 << 10) /* Enable interrupt on missed Rx packets */ |
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# define PPR_BUFCFG_RX128 (1 << 11) /* Enable Rx interrupt after 128 bytes */ |
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# define PPR_BUFCFG_TXCOL (1 << 12) /* Enable int on Tx collision ctr overflow */ |
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# define PPR_BUFCFG_MISS (1 << 13) /* Enable int on Rx miss ctr overflow */ |
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# define PPR_BUFCFG_RXDEST (1 << 15) /* Enable int on Rx dest addr match */ |
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#define PPR_LINECTL 0x0112 /* Line control */ |
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# define PPR_LINECTL_RX (1 << 6) /* Enable receiver */ |
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# define PPR_LINECTL_TX (1 << 7) /* Enable transmitter */ |
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# define PPR_LINECTL_AUIONLY (1 << 8) /* AUI interface only */ |
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# define PPR_LINECTL_AUTOAUI10BT (1 << 9) /* Autodetect AUI or 10BaseT interface */ |
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# define PPR_LINECTL_MODBACKOFFE (1 << 11) /* Enable modified backoff algorithm */ |
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# define PPR_LINECTL_POLARITYDIS (1 << 12) /* Disable Rx polarity autodetect */ |
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# define PPR_LINECTL_2PARTDEFDIS (1 << 13) /* Disable two-part defferal */ |
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# define PPR_LINECTL_LORXSQUELCH (1 << 14) /* Reduce receiver squelch threshold */ |
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#define PPR_SELFCTL 0x0114 /* Chip self control */ |
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# define PPR_SELFCTL_RESET (1 << 6) /* Self-clearing reset */ |
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# define PPR_SELFCTL_SWSUSPEND (1 << 8) /* Initiate suspend mode */ |
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# define PPR_SELFCTL_HWSLEEPE (1 << 9) /* Enable SLEEP input */ |
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# define PPR_SELFCTL_HWSTANDBYE (1 << 10) /* Enable standby mode */ |
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# define PPR_SELFCTL_HC0E (1 << 12) /* Use HCB0 for LINK LED */ |
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# define PPR_SELFCTL_HC1E (1 << 13) /* Use HCB1 for BSTATUS LED */ |
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# define PPR_SELFCTL_HCB0 (1 << 14) /* Control LINK LED if HC0E set */ |
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# define PPR_SELFCTL_HCB1 (1 << 15) /* Cntrol BSTATUS LED if HC1E set */ |
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#define PPR_BUSCTL 0x0116 /* Bus control */ |
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# define PPR_BUSCTL_RESETRXDMA (1 << 6) /* Reset RxDMA pointer */ |
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# define PPR_BUSCTL_DMAEXTEND (1 << 8) /* Extend DMA cycle */ |
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# define PPR_BUSCTL_USESA (1 << 9) /* Assert MEMCS16 on address decode */ |
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# define PPR_BUSCTL_MEMORYE (1 << 10) /* Enable memory mode */ |
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# define PPR_BUSCTL_DMABURST (1 << 11) /* Limit DMA access burst */ |
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# define PPR_BUSCTL_IOCHRDYE (1 << 12) /* Set IOCHRDY high impedence */ |
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# define PPR_BUSCTL_RXDMASIZE (1 << 13) /* Set DMA buffer size 64KB */ |
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# define PPR_BUSCTL_ENABLEIRQ (1 << 15) /* Generate interrupt on interrupt event */ |
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#define PPR_TESTCTL 0x0118 /* Test control */ |
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# define PPR_TESTCTL_DISABLELT (1 << 7) /* Disable link status */ |
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# define PPR_TESTCTL_ENDECLOOP (1 << 9) /* Internal loopback */ |
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# define PPR_TESTCTL_AUILOOP (1 << 10) /* AUI loopback */ |
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# define PPR_TESTCTL_DISBACKOFF (1 << 11) /* Disable backoff algorithm */ |
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# define PPR_TESTCTL_FDX (1 << 14) /* Enable full duplex mode */ |
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/* 0x0120 - Status and Event Registers */ |
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#define PPR_ISQ 0x0120 /* Interrupt Status Queue */ |
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#define PPR_RER 0x0124 /* Receive event */ |
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# define PPR_RER_IAHASH (1 << 6) /* Frame hash match */ |
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# define PPR_RER_DRIBBLE (1 << 7) /* Frame had 1-7 extra bits after last byte */ |
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# define PPR_RER_RXOK (1 << 8) /* Frame received with no errors */ |
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# define PPR_RER_HASHED (1 << 9) /* Frame address hashed OK */ |
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# define PPR_RER_IA (1 << 10) /* Frame address matched IA */ |
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# define PPR_RER_BROADCAST (1 << 11) /* Broadcast frame */ |
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# define PPR_RER_CRC (1 << 12) /* Frame had CRC error */ |
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# define PPR_RER_RUNT (1 << 13) /* Runt frame */ |
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# define PPR_RER_EXTRA (1 << 14) /* Frame was too long */ |
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#define PPR_TER 0x0128 /* Transmit event */ |
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# define PPR_TER_CRS (1 << 6) /* Carrier lost */ |
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# define PPR_TER_SQE (1 << 7) /* Signal Quality Error */ |
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# define PPR_TER_TXOK (1 << 8) /* Packet sent without error */ |
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# define PPR_TER_LATE (1 << 9) /* Out of window */ |
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# define PPR_TER_JABBER (1 << 10) /* Stuck transmit? */ |
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# define PPR_TER_NUMCOLLISIONS_SHIFT 11 |
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# define PPR_TER_NUMCOLLISIONS_MASK (15 << PPR_TER_NUMCOLLISIONS_SHIFT) |
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# define PPR_TER_16COLLISIONS (1 << 15) /* > 16 collisions */ |
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#define PPR_BER 0x012C /* Buffer event */ |
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# define PPR_BER_SWINT (1 << 6) /* Software interrupt */ |
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# define PPR_BER_RXDMAFRAME (1 << 7) /* Received framed DMAed */ |
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# define PPR_BER_RDY4TX (1 << 8) /* Ready for transmission */ |
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# define PPR_BER_TXUNDERRUN (1 << 9) /* Transmit underrun */ |
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# define PPR_BER_RXMISS (1 << 10) /* Received frame missed */ |
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# define PPR_BER_RX128 (1 << 11) /* 128 bytes received */ |
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# define PPR_BER_RXDEST (1 << 15) /* Received framed passed address filter */ |
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#define PPR_RXMISS 0x0130 /* Receiver miss counter */ |
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#define PPR_TXCOL 0x0132 /* Transmit collision counter */ |
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#define PPR_LINESTAT 0x0134 /* Line status */ |
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# define PPR_LINESTAT_LINKOK (1 << 7) /* Line is connected and working */ |
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# define PPR_LINESTAT_AUI (1 << 8) /* Connected via AUI */ |
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# define PPR_LINESTAT_10BT (1 << 9) /* Connected via twisted pair */ |
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# define PPR_LINESTAT_POLARITY (1 << 12) /* Line polarity OK (10BT only) */ |
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# define PPR_LINESTAT_CRS (1 << 14) /* Frame being received */ |
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#define PPR_SELFSTAT 0x0136 /* Chip self status */ |
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# define PPR_SELFSTAT_33VACTIVE (1 << 6) /* supply voltage is 3.3V */ |
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# define PPR_SELFSTAT_INITD (1 << 7) /* Chip initialization complete */ |
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# define PPR_SELFSTAT_SIBSY (1 << 8) /* EEPROM is busy */ |
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# define PPR_SELFSTAT_EEPROM (1 << 9) /* EEPROM present */ |
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# define PPR_SELFSTAT_EEPROMOK (1 << 10) /* EEPROM checks out */ |
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# define PPR_SELFSTAT_ELPRESENT (1 << 11) /* External address latch logic available */ |
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# define PPR_SELFSTAT_EESIZE (1 << 12) /* Size of EEPROM */ |
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#define PPR_BUSSTAT 0x0138 /* Bus status */ |
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# define PPR_BUSSTAT_TXBID (1 << 7) /* Tx error */ |
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# define PPR_BUSSTAT_TXRDY (1 << 8) /* Ready for Tx data */ |
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#define PPR_TDR 0x013C /* AUI Time Domain Reflectometer */ |
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/* 0x0144 - Initiate transmit registers */ |
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#define PPR_TXCOMMAND 0x0144 /* Tx Command */ |
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#define PPR_TXLENGTH 0x0146 /* Tx Length */ |
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/* 0x0150 - Address filter registers */ |
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#define PPR_LAF 0x0150 /* Logical address filter (6 bytes) */ |
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#define PPR_IA 0x0158 /* Individual address (MAC) */ |
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/* 0x0400 - Frame location registers */ |
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#define PPR_RXSTATUS 0x0400 /* Rx Status */ |
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#define PPR_RXLENGTH 0x0402 /* Rx Length */ |
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#define PPR_RXFRAMELOCATION 0x0404 /* Rx Frame Location */ |
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#define PPR_TXFRAMELOCATION 0x0a00 /* Tx Frame Location */ |
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/**************************************************************************** |
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* Public Types |
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****************************************************************************/ |
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/**************************************************************************** |
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* Public Data |
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****************************************************************************/ |
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#ifdef __cplusplus |
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#define EXTERN extern "C" |
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extern "C" { |
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#else |
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#define EXTERN extern |
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#endif |
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/**************************************************************************** |
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* Public Function Prototypes |
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****************************************************************************/ |
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#undef EXTERN |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __DRIVERS_NET_CS89x0_H */
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