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@ -112,20 +112,20 @@
@@ -112,20 +112,20 @@
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#define STM32_PLL3_DIVR_VALUE 2 |
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#elif STM32_HSECLK == 24000000U |
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// this gives 384MHz system clock
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#define STM32_PLL1_DIVM_VALUE 2 |
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#define STM32_PLL1_DIVN_VALUE 64 |
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#define STM32_PLL1_DIVM_VALUE 3 |
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#define STM32_PLL1_DIVN_VALUE 96 |
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#define STM32_PLL1_DIVP_VALUE 2 |
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#define STM32_PLL1_DIVQ_VALUE 16 |
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#define STM32_PLL1_DIVR_VALUE 2 |
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#define STM32_PLL2_DIVM_VALUE 2 |
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#define STM32_PLL2_DIVN_VALUE 13 |
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#define STM32_PLL2_DIVM_VALUE 3 |
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#define STM32_PLL2_DIVN_VALUE 19 |
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#define STM32_PLL2_DIVP_VALUE 1 |
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#define STM32_PLL2_DIVQ_VALUE 2 |
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#define STM32_PLL2_DIVR_VALUE 2 |
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#define STM32_PLL3_DIVM_VALUE 12 |
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#define STM32_PLL3_DIVN_VALUE 129 |
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#define STM32_PLL3_DIVM_VALUE 6 |
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#define STM32_PLL3_DIVN_VALUE 64 |
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#define STM32_PLL3_DIVP_VALUE 2 |
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#define STM32_PLL3_DIVQ_VALUE 2 |
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#define STM32_PLL3_DIVR_VALUE 2 |
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