From 63f39c2bd623b5ae6b10defdc4693d606e9be13d Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Thu, 1 Aug 2019 12:47:21 +1000 Subject: [PATCH] HAL_ChibiOS: fixed build of iomcu firmware --- .../AP_HAL_ChibiOS/HAL_ChibiOS_Class.cpp | 4 ++-- .../hwdef/common/stm32f1_mcuconf.h | 24 +++++++------------ 2 files changed, 10 insertions(+), 18 deletions(-) diff --git a/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.cpp b/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.cpp index 83ab8c24c6..3054aa917a 100644 --- a/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.cpp +++ b/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.cpp @@ -233,8 +233,8 @@ static void main_loop() pd.fault_thd_prio, pd.fault_icsr); } -#endif -#endif +#endif // HAL_NO_LOGGING +#endif // IOMCU_FW schedulerInstance.watchdog_pat(); diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f1_mcuconf.h b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f1_mcuconf.h index 543141b472..a7e54083d8 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f1_mcuconf.h +++ b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32f1_mcuconf.h @@ -43,30 +43,22 @@ #define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 +#elif STM32_HSECLK == 24000000U +#define STM32_SW STM32_SW_HSE +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_ADCPRE STM32_ADCPRE_DIV2 #else #error "Unsupported STM32F1xx clock frequency" #endif -#ifndef STM32_SW -#define STM32_SW STM32_SW_HSE -#endif - #ifndef STM32_HPRE #define STM32_HPRE STM32_HPRE_DIV1 #endif -#ifndef STM32_PPRE1 -#define STM32_PPRE1 STM32_PPRE1_DIV1 -#endif - -#ifndef STM32_PPRE2 -#define STM32_PPRE2 STM32_PPRE2_DIV1 -#endif - -#ifndef STM32_ADCPRE -#define STM32_ADCPRE STM32_ADCPRE_DIV2 -#endif - #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_RTCSEL STM32_RTCSEL_HSEDIV #define STM32_PVD_ENABLE FALSE