Tree: 727f8ff029

Commit Graph

3 Commits (727f8ff029aec8104747ccdee596de7ee8415604)

Author	SHA1	Message	Date
Andrew Tridgell	7ecf8981b9	SITL: added dummy SPI and make RCInput 50Hz	12 years ago
Andrew Tridgell	e020694c03	SITL: fixed build of apm1/apm2 target	12 years ago
Andrew Tridgell	0c9d37e2ee	SITL: added RCInput and RCOutput	12 years ago