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646 lines
29 KiB
646 lines
29 KiB
#pragma once |
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volatile register unsigned int __R31; |
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volatile register unsigned int __R30; |
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__far volatile char C0[0x300] __attribute__((cregister("C0", far))); |
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__far volatile char C26[0x100] __attribute__((cregister("C26", near))); /* PRUIEP */ |
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__far volatile char C4[0x100] __attribute__((cregister("C4", near))); /* PRUCFG */ |
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#define PRUCFG(_reg) \ |
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(*(volatile u32 *)((char *)C4 + (_reg))) |
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/* fast access to the registers using the constants */ |
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#define PRUCFG_REVID PRUCFG(0x0000) |
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#define PRUCFG_SYSCFG PRUCFG(0x0004) |
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#define SYSCFG_IDLE_MODE_S 0 |
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#define SYSCFG_IDLE_MODE_W 2 |
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#define SYSCFG_IDLE_MODE_M ((SYSCFG_IDLE_MODE_W - 1) << SYSCFG_IDLE_MODE_S) |
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#define SYSCFG_IDLE_MODE_FORCE (0 << SYSCFG_IDLE_MODE_S) |
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#define SYSCFG_IDLE_MODE_NO (1 << SYSCFG_IDLE_MODE_S) |
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#define SYSCFG_IDLE_MODE_SMART (2 << SYSCFG_IDLE_MODE_S) |
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#define SYSCFG_STANDBY_MODE_S 2 |
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#define SYSCFG_STANDBY_MODE_W 2 |
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#define SYSCFG_STANDBY_MODE_M ((SYSCFG_STANDBY_MODE_W - 1) << SYSCFG_STANDBY_MODE_S) |
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#define SYSCFG_STANDBY_MODE_FORCE (0 << SYSCFG_STANDBY_MODE_S) |
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#define SYSCFG_STANDBY_MODE_NO (1 << SYSCFG_STANDBY_MODE_S) |
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#define SYSCFG_STANDBY_MODE_SMART (2 << SYSCFG_STANDBY_MODE_S) |
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#define SYSCFG_STANDBY_INIT (1 << 4) |
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#define SYSCFG_SUB_MWAIT (1 << 5) |
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#define PRUCFG_SPP PRUCFG(0x0034) |
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#define SPP_PRU1_PAD_HP_EN (1 << 0) |
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#define SPP_XFR_SHIFT_EN (1 << 1) |
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#define PRUCFG_GPCFG0 PRUCFG(0x0008) |
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#define CPCFG0_PRU0_GPI_MODE_S 0 |
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#define CPCFG0_PRU0_GPI_MODE_W 2 |
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#define CPCFG0_PRU0_GPI_MODE_M ((CPCFG0_PRU0_GPI_MODE_W - 1) << CPCFG0_PRU0_GPI_MODE_S) |
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#define CPCFG0_PRU0_GPI_MODE_DIRECT (0 << CPCFG0_PRU0_GPI_MODE_S) |
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#define CPCFG0_PRU0_GPI_MODE_PARALLEL (1 << CPCFG0_PRU0_GPI_MODE_S) |
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#define CPCFG0_PRU0_GPI_MODE_SHIFT (2 << CPCFG0_PRU0_GPI_MODE_S) |
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#define CPCFG0_PRU0_GPI_MODE_MII_RT (3 << CPCFG0_PRU0_GPI_MODE_S) |
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#define CPCFG0_PRU0_GPI_CLK_MODE (1 << 2) |
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#define CPCFG0_PRU0_GPI_DIV0_S 3 |
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#define CPCFG0_PRU0_GPI_DIV0_W 5 |
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#define CPCFG0_PRU0_GPI_DIV0_M ((CPCFG0_PRU0_GPI_DIV0_W - 1) << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_1 (0 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_1_5 (1 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_2 (2 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_2_5 (3 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_3 (4 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_3_5 (5 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_4 (6 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_4_5 (7 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_5 (8 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_5_5 (9 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_6 (10 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_6_5 (11 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_7 (12 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_7_5 (13 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_8 (14 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_8_5 (15 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_9 (16 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_9_5 (17 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_10 (18 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_10_5 (19 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_11 (20 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_11_5 (21 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_12 (22 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_12_5 (23 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_13 (24 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_13_5 (25 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_14 (26 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_14_5 (27 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_15 (28 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_15_5 (29 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV0_16 (30 << CPCFG0_PRU0_GPI_DIV0_S) |
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#define CPCFG0_PRU0_GPI_DIV1_S 8 |
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#define CPCFG0_PRU0_GPI_DIV1_W 5 |
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#define CPCFG0_PRU0_GPI_DIV1_M ((CPCFG0_PRU0_GPI_DIV1_W - 1) << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_1 (0 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_1_5 (1 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_2 (2 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_2_5 (3 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_3 (4 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_3_5 (5 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_4 (6 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_4_5 (7 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_5 (8 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_5_5 (9 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_6 (10 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_6_5 (11 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_7 (12 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_7_5 (13 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_8 (14 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_8_5 (15 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_9 (16 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_9_5 (17 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_10 (18 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_10_5 (19 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_11 (20 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_11_5 (21 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_12 (22 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_12_5 (23 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_13 (24 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_13_5 (25 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_14 (26 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_14_5 (27 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_15 (28 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_15_5 (29 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_DIV1_16 (30 << CPCFG0_PRU0_GPI_DIV1_S) |
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#define CPCFG0_PRU0_GPI_S8 (1 << 13) |
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#define CPCFG0_PRU0_GPO_MODE (1 << 14) |
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#define CPCFG0_PRU0_GPO_DIV0_S 15 |
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#define CPCFG0_PRU0_GPO_DIV0_W 5 |
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#define CPCFG0_PRU0_GPO_DIV0_M ((CPCFG0_PRU0_GPO_DIV0_W - 1) << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_1 (0 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_1_5 (1 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_2 (2 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_2_5 (3 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_3 (4 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_3_5 (5 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_4 (6 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_4_5 (7 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_5 (8 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_5_5 (9 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_6 (10 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_6_5 (11 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_7 (12 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_7_5 (13 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_8 (14 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_8_5 (15 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_9 (16 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_9_5 (17 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_10 (18 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_10_5 (19 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_11 (20 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_11_5 (21 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_12 (22 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_12_5 (23 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_13 (24 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_13_5 (25 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_14 (26 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_14_5 (27 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_15 (28 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_15_5 (29 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV0_16 (30 << CPCFG0_PRU0_GPO_DIV0_S) |
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#define CPCFG0_PRU0_GPO_DIV1_S 20 |
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#define CPCFG0_PRU0_GPO_DIV1_W 5 |
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#define CPCFG0_PRU0_GPO_DIV1_M ((CPCFG0_PRU0_GPO_DIV1_W - 1) << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_1 (0 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_1_5 (1 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_2 (2 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_2_5 (3 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_3 (4 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_3_5 (5 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_4 (6 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_4_5 (7 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_5 (8 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_5_5 (9 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_6 (10 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_6_5 (11 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_7 (12 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_7_5 (13 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_8 (14 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_8_5 (15 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_9 (16 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_9_5 (17 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_10 (18 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_10_5 (19 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_11 (20 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_11_5 (21 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_12 (22 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_12_5 (23 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_13 (24 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_13_5 (25 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_14 (26 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_14_5 (27 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_15 (28 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_15_5 (29 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_DIV1_16 (30 << CPCFG0_PRU0_GPO_DIV1_S) |
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#define CPCFG0_PRU0_GPO_SH_SE (1 << 25) |
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#define PRUCFG_GPCFG1 PRUCFG(0x000C) |
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#define CPCFG0_PRU1_GPI_MODE_S 0 |
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#define CPCFG0_PRU1_GPI_MODE_W 2 |
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#define CPCFG0_PRU1_GPI_MODE_M ((CPCFG0_PRU1_GPI_MODE_W - 1) << CPCFG0_PRU1_GPI_MODE_S) |
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#define CPCFG0_PRU1_GPI_MODE_DIRECT (0 << CPCFG0_PRU1_GPI_MODE_S) |
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#define CPCFG0_PRU1_GPI_MODE_PARALLEL (1 << CPCFG0_PRU1_GPI_MODE_S) |
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#define CPCFG0_PRU1_GPI_MODE_SHIFT (2 << CPCFG0_PRU1_GPI_MODE_S) |
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#define CPCFG0_PRU1_GPI_MODE_MII_RT (3 << CPCFG0_PRU1_GPI_MODE_S) |
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#define CPCFG0_PRU1_GPI_CLK_MODE (1 << 2) |
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#define CPCFG0_PRU1_GPI_DIV0_S 3 |
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#define CPCFG0_PRU1_GPI_DIV0_W 5 |
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#define CPCFG0_PRU1_GPI_DIV0_M ((CPCFG0_PRU1_GPI_DIV0_W - 1) << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_1 (0 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_1_5 (1 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_2 (2 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_2_5 (3 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_3 (4 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_3_5 (5 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_4 (6 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_4_5 (7 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_5 (8 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_5_5 (9 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_6 (10 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_6_5 (11 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_7 (12 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_7_5 (13 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_8 (14 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_8_5 (15 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_9 (16 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_9_5 (17 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_10 (18 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_10_5 (19 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_11 (20 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_11_5 (21 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_12 (22 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_12_5 (23 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_13 (24 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_13_5 (25 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_14 (26 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_14_5 (27 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_15 (28 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_15_5 (29 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV0_16 (30 << CPCFG0_PRU1_GPI_DIV0_S) |
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#define CPCFG0_PRU1_GPI_DIV1_S 8 |
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#define CPCFG0_PRU1_GPI_DIV1_W 5 |
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#define CPCFG0_PRU1_GPI_DIV1_M ((CPCFG0_PRU1_GPI_DIV1_W - 1) << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_1 (0 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_1_5 (1 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_2 (2 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_2_5 (3 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_3 (4 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_3_5 (5 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_4 (6 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_4_5 (7 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_5 (8 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_5_5 (9 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_6 (10 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_6_5 (11 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_7 (12 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_7_5 (13 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_8 (14 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_8_5 (15 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_9 (16 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_9_5 (17 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_10 (18 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_10_5 (19 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_11 (20 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_11_5 (21 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_12 (22 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_12_5 (23 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_13 (24 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_13_5 (25 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_14 (26 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_14_5 (27 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_15 (28 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_15_5 (29 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_DIV1_16 (30 << CPCFG0_PRU1_GPI_DIV1_S) |
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#define CPCFG0_PRU1_GPI_S8 (1 << 13) |
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#define CPCFG0_PRU1_GPO_MODE (1 << 14) |
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#define CPCFG0_PRU1_GPO_DIV0_S 15 |
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#define CPCFG0_PRU1_GPO_DIV0_W 5 |
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#define CPCFG0_PRU1_GPO_DIV0_M ((CPCFG0_PRU1_GPO_DIV0_W - 1) << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_1 (0 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_1_5 (1 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_2 (2 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_2_5 (3 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_3 (4 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_3_5 (5 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_4 (6 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_4_5 (7 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_5 (8 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_5_5 (9 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_6 (10 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_6_5 (11 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_7 (12 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_7_5 (13 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_8 (14 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_8_5 (15 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_9 (16 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_9_5 (17 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_10 (18 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_10_5 (19 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_11 (20 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_11_5 (21 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_12 (22 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_12_5 (23 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_13 (24 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_13_5 (25 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_14 (26 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_14_5 (27 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_15 (28 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_15_5 (29 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV0_16 (30 << CPCFG0_PRU1_GPO_DIV0_S) |
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#define CPCFG0_PRU1_GPO_DIV1_S 20 |
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#define CPCFG0_PRU1_GPO_DIV1_W 5 |
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#define CPCFG0_PRU1_GPO_DIV1_M ((CPCFG0_PRU1_GPO_DIV1_W - 1) << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_1 (0 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_1_5 (1 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_2 (2 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_2_5 (3 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_3 (4 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_3_5 (5 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_4 (6 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_4_5 (7 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_5 (8 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_5_5 (9 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_6 (10 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_6_5 (11 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_7 (12 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_7_5 (13 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_8 (14 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_8_5 (15 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_9 (16 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_9_5 (17 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_10 (18 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_10_5 (19 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_11 (20 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_11_5 (21 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_12 (22 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_12_5 (23 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_13 (24 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_13_5 (25 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_14 (26 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_14_5 (27 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_15 (28 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_15_5 (29 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_DIV1_16 (30 << CPCFG0_PRU1_GPO_DIV1_S) |
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#define CPCFG0_PRU1_GPO_SH_SE (1 << 25) |
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#define PRUCFG_CGR PRUCFG(0x0010) |
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#define PRUCFG_ISRP PRUCFG(0x0014) |
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#define PRUCFG_ISP PRUCFG(0x0018) |
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#define PRUCFG_IESP PRUCFG(0x001C) |
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#define PRUCFG_PMAO PRUCFG(0x0028) |
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#define PMAO_PMAO_PRU0 (1 << 0) |
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#define PMAO_PMAO_PRU1 (1 << 1) |
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#define PRUCFG_MII_RT PRUCFG(0x002C) |
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#define PRUCFG_IEPCLK PRUCFG(0x0030) |
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#define PRUCFG_PINMX PRUCFG(0x0040) |
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#define PINTC(_reg) \ |
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(*(volatile u32 *)((char *)C0 + (_reg))) |
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#define PINTC_REVID PINTC(0x0000) |
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#define PINTC_CR PINTC(0x0004) |
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#define PINTC_GER PINTC(0x0010) |
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#define PINTC_GNLR PINTC(0x001C) |
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#define PINTC_SISR PINTC(0x0020) |
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#define PINTC_SICR PINTC(0x0024) |
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#define PINTC_EISR PINTC(0x0028) |
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#define PINTC_EICR PINTC(0x002C) |
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#define PINTC_HIEISR PINTC(0x0034) |
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#define PINTC_HIDISR PINTC(0x0038) |
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#define PINTC_GPIR PINTC(0x0080) |
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#define PINTC_SRSR0 PINTC(0x0200) |
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#define PINTC_SRSR1 PINTC(0x0204) |
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#define PINTC_SECR0 PINTC(0x0280) |
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#define PINTC_SECR1 PINTC(0x0284) |
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#define PINTC_ESR0 PINTC(0x0300) |
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#define PINTC_ESR1 PINTC(0x0304) |
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#define PINTC_ECR0 PINTC(0x0380) |
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#define PINTC_ECR1 PINTC(0x0384) |
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#define PINTC_CMR0 PINTC(0x0400) |
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#define PINTC_CMR1 PINTC(0x0404) |
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#define PINTC_CMR2 PINTC(0x0408) |
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#define PINTC_CMR3 PINTC(0x040C) |
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#define PINTC_CMR4 PINTC(0x0410) |
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#define PINTC_CMR5 PINTC(0x0414) |
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#define PINTC_CMR6 PINTC(0x0418) |
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#define PINTC_CMR7 PINTC(0x041C) |
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#define PINTC_CMR8 PINTC(0x0420) |
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#define PINTC_CMR9 PINTC(0x0424) |
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#define PINTC_CMR10 PINTC(0x0428) |
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#define PINTC_CMR11 PINTC(0x042C) |
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#define PINTC_CMR12 PINTC(0x0430) |
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#define PINTC_CMR13 PINTC(0x0434) |
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#define PINTC_CMR14 PINTC(0x0438) |
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#define PINTC_CMR15 PINTC(0x043C) |
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#define PINTC_HMR0 PINTC(0x0800) |
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#define PINTC_HMR1 PINTC(0x0804) |
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#define PINTC_HMR2 PINTC(0x0808) |
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#define PINTC_HIPIR0 PINTC(0x0900) |
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#define PINTC_HIPIR1 PINTC(0x0904) |
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#define PINTC_HIPIR2 PINTC(0x0908) |
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#define PINTC_HIPIR3 PINTC(0x090C) |
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#define PINTC_HIPIR4 PINTC(0x0910) |
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#define PINTC_HIPIR5 PINTC(0x0914) |
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#define PINTC_HIPIR6 PINTC(0x0918) |
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#define PINTC_HIPIR7 PINTC(0x091C) |
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#define PINTC_HIPIR8 PINTC(0x0920) |
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#define PINTC_HIPIR9 PINTC(0x0924) |
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#define PINTC_SIPR0 PINTC(0x0D00) |
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#define PINTC_SIPR1 PINTC(0x0D04) |
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#define PINTC_SITR0 PINTC(0x0D80) |
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#define PINTC_SITR1 PINTC(0x0D84) |
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#define PINTC_HINLR0 PINTC(0x1100) |
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#define PINTC_HINLR1 PINTC(0x1104) |
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#define PINTC_HINLR2 PINTC(0x1108) |
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#define PINTC_HINLR3 PINTC(0x110C) |
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#define PINTC_HINLR4 PINTC(0x1110) |
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#define PINTC_HINLR5 PINTC(0x1114) |
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#define PINTC_HINLR6 PINTC(0x1118) |
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#define PINTC_HINLR7 PINTC(0x111C) |
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#define PINTC_HINLR8 PINTC(0x1120) |
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#define PINTC_HINLR9 PINTC(0x1124) |
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#define PINTC_HIER PINTC(0x1500) |
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/* PRU Industrial Ethernet Peripheral */ |
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#define PIEP(_reg) \ |
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(*(volatile u32 *)((char *)C26 + (_reg))) |
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#define PIEP_GLOBAL_CFG PIEP(0x0000) |
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#define GLOBAL_CFG_CNT_ENABLE (1 << 0) |
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#define GLOBAL_CFG_DEFAULT_INC_S 4 |
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#define GLOBAL_CFG_DEFAULT_INC_W 4 |
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#define GLOBAL_CFG_DEFAULT_INC_M ((GLOBAL_CFG_DEFAULT_INC_W - 1) << GLOBAL_CFG_DEFAULT_INC_S) |
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#define GLOBAL_CFG_DEFAULT_INC(x) (((x) << GLOBAL_CFG_DEFAULT_INC_S) & GLOBAL_CFG_DEFAULT_INC_M) |
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#define GLOBAL_CFG_CMP_INC_S 8 |
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#define GLOBAL_CFG_CMP_INC_W 12 |
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#define GLOBAL_CFG_CMP_INC_M ((GLOBAL_CFG_CMP_INC_W - 1) << GLOBAL_CFG_CMP_INC_S) |
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#define GLOBAL_CFG_CMP_INC(x) (((x) << GLOBAL_CFG_CMP_INC_S) & GLOBAL_CFG_CMP_INC_M) |
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#define PIEP_GLOBAL_STATUS PIEP(0x0004) |
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#define GLOBAL_STATUS_CNT_OVF (1 << 0) |
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#define PIEP_COMPEN PIEP(0x0008) |
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#define PIEP_COUNT PIEP(0x000C) |
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#define PIEP_CMP_CFG PIEP(0x0040) |
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#define CMP_CFG_CMP0_RST_CNT_EN (1 << 0) |
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#define CMP_CFG_CMP_EN_S 1 |
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#define CMP_CFG_CMP_EN_W 8 |
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#define CMP_CFG_CMP_EN_M ((CMP_CFG_CMP_EN_W - 1) << CMP_CFG_CMP_EN_S) |
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#define CMP_CFG_CMP_EN(x) ((1 << ((x) + CMP_CFG_CMP_EN_S)) & CMP_CFG_CMP_EN_M) |
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#define PIEP_CMP_STATUS PIEP(0x0044) |
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#define CMD_STATUS_CMP_HIT_S 0 |
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#define CMD_STATUS_CMP_HIT_W 8 |
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#define CMD_STATUS_CMP_HIT_M ((CMD_STATUS_CMP_HIT_W - 1) << CMD_STATUS_CMP_HIT_S) |
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#define CMD_STATUS_CMP_HIT(x) ((1 << ((x) + CMD_STATUS_CMP_HIT_S)) & CMD_STATUS_CMP_HIT_M) |
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#define PIEP_CMP_CMP0 PIEP(0x0048) |
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#define PIEP_CMP_CMP1 PIEP(0x004C) |
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#define PIEP_CMP_CMP2 PIEP(0x0050) |
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#define PIEP_CMP_CMP3 PIEP(0x0054) |
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#define PIEP_CMP_CMP4 PIEP(0x0058) |
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#define PIEP_CMP_CMP5 PIEP(0x005C) |
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#define PIEP_CMP_CMP6 PIEP(0x0060) |
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#define PIEP_CMP_CMP7 PIEP(0x0064) |
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#define PIEP_CMP_CMP(x) PIEP(0x0048 + ((x) << 2)) |
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#if defined(PRU0) || defined(PRU1) |
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#ifdef PRU0 |
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#define PCTRL(_reg) \ |
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(*(volatile u32 *)((char *)0x22000 + (_reg))) |
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#define PCTRL_OTHER(_reg) \ |
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(*(volatile u32 *)((char *)0x24000 + (_reg))) |
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#else |
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#define PCTRL(_reg) \ |
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(*(volatile u32 *)((char *)0x24000 + (_reg))) |
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#define PCTRL_OTHER(_reg) \ |
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(*(volatile u32 *)((char *)0x22000 + (_reg))) |
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#endif |
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#define PCTRL_CONTROL PCTRL(0x0000) |
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#define CONTROL_SOFT_RST_N (1 << 0) |
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#define CONTROL_ENABLE (1 << 1) |
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#define CONTROL_SLEEPING (1 << 2) |
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#define CONTROL_COUNTER_ENABLE (1 << 3) |
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#define CONTROL_SINGLE_STEP (1 << 8) |
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#define CONTROL_RUNSTATE (1 << 15) |
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#define PCTRL_STATUS PCTRL(0x0004) |
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#define PCTRL_WAKEUP_EN PCTRL(0x0008) |
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#define PCTRL_CYCLE PCTRL(0x000C) |
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#define PCTRL_STALL PCTRL(0x0010) |
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#define PCTRL_CTBIR0 PCTRL(0x0020) |
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#define PCTRL_CTBIR1 PCTRL(0x0024) |
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#define PCTRL_CTPPR0 PCTRL(0x0028) |
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#define PCTRL_CTPPR1 PCTRL(0x002C) |
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/* we can't access our debug registers (since we have to be stopped) */ |
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#ifdef PRU0 |
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#define PDBG_OTHER(_reg) \ |
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(*(volatile u32 *)((char *)0x24400 + (_reg))) |
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#else |
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#define PDBG_OTHER(_reg) \ |
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(*(volatile u32 *)((char *)0x22400 + (_reg))) |
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#endif |
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#endif |
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/* secondary access by C28 (which must point to 0x20200 */ |
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#define PINTC_0200(_reg) \ |
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(*(volatile u32 *)((char *)C28 + ((_reg) - 0x200))) |
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#define SIGNAL_EVENT(x) \ |
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do { \ |
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__R31 = (1 << 5) | ((x) - 16); \ |
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} while(0) |
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#ifndef PRU_CLK |
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/* default PRU clock (200MHz) */ |
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#define PRU_CLK 200000000 |
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#endif |
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/* NOTE: Do no use it for larger than 5 secs */ |
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#define PRU_200MHz_sec(x) ((u32)(((x) * 200000000))) |
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#define PRU_200MHz_ms(x) ((u32)(((x) * 200000))) |
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#define PRU_200MHz_ms_err(x) 0 |
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#define PRU_200MHz_us(x) ((u32)(((x) * 200))) |
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#define PRU_200MHz_us_err(x) 0 |
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#define PRU_200MHz_ns(x) ((u32)(((x) * 2) / 10)) |
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#define PRU_200MHz_ns_err(x) ((u32)(((x) * 2) % 10)) |
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#if PRU_CLK != 200000000 |
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/* NOTE: Do no use it for larger than 5 secs */ |
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#define PRU_sec(x) ((u32)(((u64)(x) * PRU_CLK))) |
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#define PRU_ms(x) ((u32)(((u64)(x) * PRU_CLK) / 1000)) |
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#define PRU_ms_err(x) ((u32)(((u64)(x) * PRU_CLK) % 1000)) |
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#define PRU_us(x) ((u32)(((u64)(x) * PRU_CLK) / 1000000)) |
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#define PRU_us_err(x) ((u32)(((u64)(x) * PRU_CLK) % 1000000)) |
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#define PRU_ns(x) ((u32)(((u64)(x) * PRU_CLK) / 1000000000)) |
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#define PRU_ns_err(x) ((u32)(((u64)(x) * PRU_CLK) % 1000000000)) |
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#else |
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/* NOTE: Do no use it for larger than 5 secs */ |
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#define PRU_sec(x) PRU_200MHz_sec(x) |
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#define PRU_ms(x) PRU_200MHz_ms(x) |
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#define PRU_ms_err(x) PRU_200MHz_ms_err(x) |
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#define PRU_us(x) PRU_200MHz_us(x) |
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#define PRU_us_err(x) PRU_200MHz_us_err(x) |
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#define PRU_ns(x) PRU_200MHz_ns(x) |
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#define PRU_ns_err(x) PRU_200MHz_ns_err(x) |
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#endif |
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#define DPRAM_SHARED 0x00010000 |
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/* event definitions */ |
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#define SYSEV_ARM_TO_PRU0 21 |
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#define SYSEV_ARM_TO_PRU1 22 |
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#define SYSEV_PRU0_TO_ARM 19 |
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#define SYSEV_PRU0_TO_PRU1 17 |
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#define SYSEV_PRU1_TO_ARM 20 |
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#define SYSEV_PRU1_TO_PRU0 19 |
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/* for communication with the host we have another set of events */ |
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#define SYSEV_VR_ARM_TO_PRU0 24 |
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#define SYSEV_VR_PRU0_TO_ARM 25 |
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#define SYSEV_VR_ARM_TO_PRU1 26 |
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#define SYSEV_VR_PRU1_TO_ARM 27 |
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#define pru0_signal() (__R31 & (1U << 30)) |
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#define pru1_signal() (__R31 & (1U << 31)) |
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#ifdef PRU0 |
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#define pru_signal() pru0_signal() |
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#define SYSEV_OTHER_PRU_TO_THIS_PRU SYSEV_PRU1_TO_PRU0 |
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#define SYSEV_ARM_TO_THIS_PRU SYSEV_ARM_TO_PRU0 |
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#define SYSEV_THIS_PRU_TO_OTHER_PRU SYSEV_PRU0_TO_PRU1 |
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#define SYSEV_THIS_PRU_TO_ARM SYSEV_PRU0_TO_ARM |
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#define SYSEV_VR_ARM_TO_THIS_PRU SYSEV_VR_ARM_TO_PRU0 |
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#define SYSEV_VR_THIS_PRU_TO_ARM SYSEV_VR_PRU0_TO_ARM |
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#endif |
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#ifdef PRU1 |
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#define pru_signal() pru1_signal() |
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#define SYSEV_OTHER_PRU_TO_THIS_PRU SYSEV_PRU0_TO_PRU1 |
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#define SYSEV_ARM_TO_THIS_PRU SYSEV_ARM_TO_PRU1 |
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#define SYSEV_THIS_PRU_TO_OTHER_PRU SYSEV_PRU1_TO_PRU0 |
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#define SYSEV_THIS_PRU_TO_ARM SYSEV_PRU1_TO_ARM |
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#define SYSEV_VR_ARM_TO_THIS_PRU SYSEV_VR_ARM_TO_PRU1 |
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#define SYSEV_VR_THIS_PRU_TO_ARM SYSEV_VR_PRU1_TO_ARM |
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#endif |
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/* all events < 32 */ |
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#define SYSEV_THIS_PRU_INCOMING_MASK \ |
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(BIT(SYSEV_ARM_TO_THIS_PRU) | \ |
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BIT(SYSEV_OTHER_PRU_TO_THIS_PRU) | \ |
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BIT(SYSEV_VR_ARM_TO_THIS_PRU)) |
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#define DELAY_CYCLES(x) \ |
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do { \ |
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unsigned int t = (x) >> 1; \ |
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do { \ |
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__asm(" "); \ |
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} while (--t); \ |
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} while(0) |
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#ifndef BIT |
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#define BIT(x) (1U << (x)) |
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#endif |
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/* access to the resources of the other PRU (halt it and have your way) */ |
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#if defined(PRU0) || defined(PRU1) |
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static inline void pru_other_halt(void) |
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{ |
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PCTRL_OTHER(0x0000) &= ~CONTROL_ENABLE; /* clear enable */ |
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/* loop until RUNSTATE clears */ |
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while ((PCTRL_OTHER(0x0000) & CONTROL_RUNSTATE) != 0) |
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; |
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} |
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static inline void pru_other_resume(void) |
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{ |
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PCTRL_OTHER(0x0000) |= CONTROL_ENABLE; /* set enable */ |
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} |
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static inline u32 pru_other_read_reg(u16 reg) |
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{ |
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u32 val; |
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reg <<= 2; /* multiply by 4 */ |
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pru_other_halt(); |
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val = PDBG_OTHER(reg); |
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pru_other_resume(); |
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return val; |
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} |
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static inline void pru_other_write_reg(u16 reg, u32 val) |
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{ |
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reg <<= 2; /* multiply by 4 */ |
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pru_other_halt(); |
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PDBG_OTHER(reg) = val; |
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pru_other_resume(); |
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} |
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static inline void pru_other_and_or_reg(u16 reg, u32 andmsk, u32 ormsk) |
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{ |
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reg <<= 2; /* multiply by 4 */ |
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pru_other_halt(); |
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PDBG_OTHER(reg) = (PDBG_OTHER(reg) & andmsk) | ormsk; |
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pru_other_resume(); |
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} |
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#endif
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