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393 lines
9.3 KiB
393 lines
9.3 KiB
/* |
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio |
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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http://www.apache.org/licenses/LICENSE-2.0 |
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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/* |
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* ST32F429xI memory setup. |
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* Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. |
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*/ |
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MEMORY |
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{ |
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flash : org = 0x08004000, len = 2032K |
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ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ |
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ram1 : org = 0x20000000, len = 112k /* SRAM1 */ |
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ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ |
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ram3 : org = 0x20020000, len = 64k /* SRAM3 */ |
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ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ |
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ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ |
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ram6 : org = 0x00000000, len = 0 |
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ram7 : org = 0x00000000, len = 0 |
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} |
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/* RAM region to be used for Main stack. This stack accommodates the processing |
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of all exceptions and interrupts*/ |
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REGION_ALIAS("MAIN_STACK_RAM", ram0); |
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/* RAM region to be used for the process stack. This is the stack used by |
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the main() function.*/ |
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REGION_ALIAS("PROCESS_STACK_RAM", ram0); |
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/* RAM region to be used for data segment.*/ |
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REGION_ALIAS("DATA_RAM", ram0); |
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/* RAM region to be used for BSS segment.*/ |
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REGION_ALIAS("BSS_RAM", ram0); |
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/* RAM region to be used for the default heap.*/ |
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REGION_ALIAS("HEAP_RAM", ram0); |
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__ram0_start__ = ORIGIN(ram0); |
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__ram0_size__ = LENGTH(ram0); |
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__ram0_end__ = __ram0_start__ + __ram0_size__; |
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__ram1_start__ = ORIGIN(ram1); |
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__ram1_size__ = LENGTH(ram1); |
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__ram1_end__ = __ram1_start__ + __ram1_size__; |
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__ram2_start__ = ORIGIN(ram2); |
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__ram2_size__ = LENGTH(ram2); |
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__ram2_end__ = __ram2_start__ + __ram2_size__; |
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__ram3_start__ = ORIGIN(ram3); |
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__ram3_size__ = LENGTH(ram3); |
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__ram3_end__ = __ram3_start__ + __ram3_size__; |
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__ram4_start__ = ORIGIN(ram4); |
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__ram4_size__ = LENGTH(ram4); |
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__ram4_end__ = __ram4_start__ + __ram4_size__; |
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__ram5_start__ = ORIGIN(ram5); |
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__ram5_size__ = LENGTH(ram5); |
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__ram5_end__ = __ram5_start__ + __ram5_size__; |
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__ram6_start__ = ORIGIN(ram6); |
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__ram6_size__ = LENGTH(ram6); |
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__ram6_end__ = __ram6_start__ + __ram6_size__; |
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__ram7_start__ = ORIGIN(ram7); |
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__ram7_size__ = LENGTH(ram7); |
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__ram7_end__ = __ram7_start__ + __ram7_size__; |
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ENTRY(Reset_Handler) |
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SECTIONS |
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{ |
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. = 0; |
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_text = .; |
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startup : ALIGN(16) SUBALIGN(16) |
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{ |
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KEEP(*(.vectors)) |
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} > flash |
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constructors : ALIGN(4) SUBALIGN(4) |
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{ |
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__init_array_start = .; |
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KEEP(*(SORT(.init_array.*))) |
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KEEP(*(.init_array)) |
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__init_array_end = .; |
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} > flash |
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destructors : ALIGN(4) SUBALIGN(4) |
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{ |
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__fini_array_start = .; |
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KEEP(*(.fini_array)) |
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KEEP(*(SORT(.fini_array.*))) |
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__fini_array_end = .; |
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} > flash |
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.text : ALIGN(16) SUBALIGN(16) |
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{ |
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*(.text) |
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*(.text.*) |
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*(.rodata) |
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*(.rodata.*) |
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*(.glue_7t) |
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*(.glue_7) |
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*(.gcc*) |
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} > flash |
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.ARM.extab : |
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{ |
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*(.ARM.extab* .gnu.linkonce.armextab.*) |
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} > flash |
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.ARM.exidx : { |
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__exidx_start = .; |
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*(.ARM.exidx* .gnu.linkonce.armexidx.*) |
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__exidx_end = .; |
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} > flash |
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.eh_frame_hdr : |
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{ |
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*(.eh_frame_hdr) |
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} > flash |
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.eh_frame : ONLY_IF_RO |
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{ |
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*(.eh_frame) |
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} > flash |
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.textalign : ONLY_IF_RO |
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{ |
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. = ALIGN(8); |
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} > flash |
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/* Legacy symbol, not used anywhere.*/ |
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. = ALIGN(4); |
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PROVIDE(_etext = .); |
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/* Special section for exceptions stack.*/ |
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.mstack : |
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{ |
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. = ALIGN(8); |
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__main_stack_base__ = .; |
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. += __main_stack_size__; |
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. = ALIGN(8); |
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__main_stack_end__ = .; |
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} > MAIN_STACK_RAM |
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/* Special section for process stack.*/ |
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.pstack : |
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{ |
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__process_stack_base__ = .; |
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__main_thread_stack_base__ = .; |
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. += __process_stack_size__; |
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. = ALIGN(8); |
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__process_stack_end__ = .; |
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__main_thread_stack_end__ = .; |
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} > PROCESS_STACK_RAM |
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.data : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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PROVIDE(_textdata = LOADADDR(.data)); |
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PROVIDE(_data = .); |
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_textdata_start = LOADADDR(.data); |
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_data_start = .; |
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*(.data) |
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*(.data.*) |
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*(.ramtext) |
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. = ALIGN(4); |
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PROVIDE(_edata = .); |
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_data_end = .; |
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} > DATA_RAM AT > flash |
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.bss (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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_bss_start = .; |
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*(.bss) |
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*(.bss.*) |
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*(COMMON) |
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. = ALIGN(4); |
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_bss_end = .; |
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PROVIDE(end = .); |
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} > BSS_RAM |
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.ram0_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram0_init_text__ = LOADADDR(.ram0_init); |
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__ram0_init__ = .; |
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*(.ram0_init) |
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*(.ram0_init.*) |
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. = ALIGN(4); |
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} > ram0 AT > flash |
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.ram0 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram0_clear__ = .; |
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*(.ram0_clear) |
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*(.ram0_clear.*) |
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. = ALIGN(4); |
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__ram0_noinit__ = .; |
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*(.ram0) |
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*(.ram0.*) |
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. = ALIGN(4); |
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__ram0_free__ = .; |
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} > ram0 |
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.ram1_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram1_init_text__ = LOADADDR(.ram1_init); |
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__ram1_init__ = .; |
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*(.ram1_init) |
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*(.ram1_init.*) |
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. = ALIGN(4); |
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} > ram1 AT > flash |
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.ram1 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram1_clear__ = .; |
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*(.ram1_clear) |
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*(.ram1_clear.*) |
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. = ALIGN(4); |
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__ram1_noinit__ = .; |
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*(.ram1) |
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*(.ram1.*) |
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. = ALIGN(4); |
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__ram1_free__ = .; |
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} > ram1 |
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.ram2_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram2_init_text__ = LOADADDR(.ram2_init); |
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__ram2_init__ = .; |
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*(.ram2_init) |
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*(.ram2_init.*) |
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. = ALIGN(4); |
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} > ram2 AT > flash |
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.ram2 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram2_clear__ = .; |
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*(.ram2_clear) |
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*(.ram2_clear.*) |
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. = ALIGN(4); |
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__ram2_noinit__ = .; |
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*(.ram2) |
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*(.ram2.*) |
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. = ALIGN(4); |
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__ram2_free__ = .; |
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} > ram2 |
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.ram3_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram3_init_text__ = LOADADDR(.ram3_init); |
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__ram3_init__ = .; |
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*(.ram3_init) |
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*(.ram3_init.*) |
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. = ALIGN(4); |
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} > ram3 AT > flash |
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.ram3 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram3_clear__ = .; |
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*(.ram3_clear) |
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*(.ram3_clear.*) |
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. = ALIGN(4); |
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__ram3_noinit__ = .; |
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*(.ram3) |
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*(.ram3.*) |
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. = ALIGN(4); |
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__ram3_free__ = .; |
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} > ram3 |
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.ram4_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram4_init_text__ = LOADADDR(.ram4_init); |
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__ram4_init__ = .; |
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*(.ram4_init) |
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*(.ram4_init.*) |
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. = ALIGN(4); |
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} > ram4 AT > flash |
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.ram4 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram4_clear__ = .; |
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*(.ram4_clear) |
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*(.ram4_clear.*) |
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. = ALIGN(4); |
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__ram4_noinit__ = .; |
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*(.ram4) |
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*(.ram4.*) |
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. = ALIGN(4); |
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__ram4_free__ = .; |
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} > ram4 |
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.ram5_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram5_init_text__ = LOADADDR(.ram5_init); |
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__ram5_init__ = .; |
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*(.ram5_init) |
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*(.ram5_init.*) |
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. = ALIGN(4); |
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} > ram5 AT > flash |
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.ram5 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram5_clear__ = .; |
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*(.ram5_clear) |
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*(.ram5_clear.*) |
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. = ALIGN(4); |
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__ram5_noinit__ = .; |
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*(.ram5) |
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*(.ram5.*) |
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. = ALIGN(4); |
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__ram5_free__ = .; |
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} > ram5 |
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.ram6_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram6_init_text__ = LOADADDR(.ram6_init); |
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__ram6_init__ = .; |
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*(.ram6_init) |
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*(.ram6_init.*) |
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. = ALIGN(4); |
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} > ram6 AT > flash |
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.ram6 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram6_clear__ = .; |
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*(.ram6_clear) |
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*(.ram6_clear.*) |
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. = ALIGN(4); |
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__ram6_noinit__ = .; |
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*(.ram6) |
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*(.ram6.*) |
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. = ALIGN(4); |
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__ram6_free__ = .; |
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} > ram6 |
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.ram7_init : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram7_init_text__ = LOADADDR(.ram7_init); |
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__ram7_init__ = .; |
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*(.ram7_init) |
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*(.ram7_init.*) |
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. = ALIGN(4); |
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} > ram7 AT > flash |
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.ram7 (NOLOAD) : ALIGN(4) |
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{ |
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. = ALIGN(4); |
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__ram7_clear__ = .; |
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*(.ram7_clear) |
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*(.ram7_clear.*) |
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. = ALIGN(4); |
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__ram7_noinit__ = .; |
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*(.ram7) |
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*(.ram7.*) |
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. = ALIGN(4); |
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__ram7_free__ = .; |
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} > ram7 |
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/* The default heap uses the (statically) unused part of a RAM section.*/ |
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.heap (NOLOAD) : |
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{ |
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. = ALIGN(8); |
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__heap_base__ = .; |
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. = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM); |
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__heap_end__ = .; |
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} > HEAP_RAM |
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}
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